Comparator ASIC and Cathode FE Card 1999

Comparator ASIC "COMP-C"

The comparator ASIC converts the analog signals from the preamps into 1/2-strip digital information. The ASIC receives the analog Buckeye outputs with nominal 1 mV/fC transfer function and 150ns peaking time (typical chamber signals are 100 fC). The Comparator ASIC is AC-coupled and the first stage has 4x buffer amplifiers to reduce the effect of comparator offsets. Each ASIC covers 16 strips.  Actually, 18 analog signals are input in order to handle the boundaries between chips seamlessly.

The ASIC produced in 1999 introduces data compression to reduce the number of outputs from 32 to 8. A factor of 4 compression beyond simple half-strip bits is achieved. We take advantage of the slow development of cathode signals (~150 ns peak time and fall time) plus the fact that there can only be one half-strip hit within any two strips (since the hit strip has to have signal larger than either of its neighbors).

ASIC design:

• Santiard's description of the Comparator ASIC "COMP-C" with results from testing.
• Comparator digital control bits are:
• Peaking Time (3 bits): 25ns to 200ns in 25ns steps
• Peaking Mode (2 bits): Mode 0 requires Qn>Qth (threshold) for only 1 clock, Mode 1 requires Qn>Qth for 1st and nth clock, Mode 2 requires Qn>Qth for all clocks
• Comparator 4:1 lossless data compression timing diagram (PostScript).
• Radiation testing: results were good. The ASIC chips were tested for Latchups and Single Event Upsets (SEU's) at the UC Davis 63 MeV p Facility. The detailed radiation test procedure and results can be found here.

Comparator circuits on CFEB board built by OSU:

• A detailed description of the bits and links between the cathode front-end board and the LCT board.
• A text description of the project
• A cartoon of the comparator-related components (PostScript format).

ASIC Testing and production information:

• CERN chip testing plan has been developed for pre-production quantities. Full production quantities will require commercial testing.

• Here is a diagram of the comparator ASIC layout:

• Here is a picture of the ASIC with and without its package, next to a mm scale:

• Here is a picture of the packaged comparator ASIC:

• (Outdated!) 1997 version of comparator data compression logic shown below can actually be read in a Postscript file, a huge GIF file (readable) or a large GIF file (barely readable).

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