CLCT48 and ALCT48 and Associated Cards

Cathode LCT Cards

Here is a picture of the 48-channel LCT card developed for both cathode and anode triggering at the 1998 test beam:

There is also a

• A block diagram of the LCT prototype and its interfaces
• A detailed "schematic" LCT board layout including the cathode mezzanine card (PostScript).
• An "xray" version of the LCT board layout (PostScript).

A very detailed view of the cathode LCT card logic can be found here (PostScript). A similar view of the anode version (same board and chips, different software) can be found here (PostScript). The important pieces of this card, designed by JK, are:

• A single Altera 10K50 FPGA chip, called the "front" or "latch" gate array, inputs 96 half-strip bits, ORs then to make distrip bits, and then presents either (24) distrip bits to the RAM array for pre-triggering and high-angle (low-momentum) muon triggering, or half-strip bits to the RAM array for low-angle (high-momentum) muon triggering. This chip is mounted in a 403-pin grid array socket. We can download trigger test patterns at the input of the front gate array to test logic and RAM table configurations. The front gate array also supplies addresses to the RAMs during downloading and RAM readout. A slightly outdated view (not very detailed) of this array is found here (Postscript).
• Eight Motorola MCM6726D static RAM chips, which are 128K x 8bits, 10ns access time, which look up the trigger patterns for tracks. (5v versions)
• A single Altera 10K20 FPGA chip, called the "rear" or "priority encoder" gate array, which inputs the track patterns found from the RAMs and priority encodes them to find the "best" track. This chip is mounted in a 240-pin power quad flat pack and is socketed. Also included in this chip is the formatter which assembles data to be sent to the Trigger Motherboard, and the controller, which contains a number of state machines handling various functions such as downloading, running, and readout. An Altera diagram of the rear gate array logic can be found here (PostScript).
• A single Altera 10K20 FPGA chip which serves as CAMAC interface, also in a 240-pin quad flat pack. We also include a FIFO which serves as a fake trigger motherboard, accumulating the output LCT information from sequential triggers. This chip controls a bi-directional command bus and is the only chip which needs to be changed when a real DAQ/command interface is defined.
• A National Instruments DS90CR283 channel-link transmitter chip, which serves as the link to the Trigger Motherboard. This chip inputs 28 TTL bits at up to 66 MHz and outputs them as LVDS differential levels on 5 twisted pairs.
• One Altera EPC1 serial EPROM for each FPGA which is used to load the initial state of the FPGA logic.
• One 128K x 8 bit non-volatile RAM (NVRAM), which is used to initialize the RAM chips. This is a Dallas Semiconductor DS1245. It has an on-board battery with 10-year lifetime.
• Front-panel LEDs representing: pretrigger, module address by CAMAC, and external trigger in.
• 40 MHz on-board crystal oscillator clock source for testing. In normal operation the clock source is external to the board.
• About two TTL "glue" logic chips to choose among various clock sources.
• One TTL buffer chip plus jumpers in order to adjust synchronization between front and rear gate array clocks in steps of about 2 ns.
• About 8 passive TTL buffer chips for connection to the CAMAC backplane.
• NIM inputs: external clock, external trigger.

The board is initialized in the following sequence:

1. Each on-board EPROM clocks its data into the associated FPGAs to configure them at power-up (50-250ms).
2. Through CAMAC, the controller FPGA logic is instructed to perform an initialization sequence for the RAMs. During this sequence, data goes from the on-board EEPROM into the rear gate array and thence to the RAMs (less than 30ms).
3. The Altera FPGA logic can be re-downloaded (or editted) by a "Byte-Blaster" serial connection to a PC (maybe a minute); or alternatively, from CAMAC (except for the CAMAC interface FPGA, of course...). Through CAMAC, it might take a while, even hours, depending on how sluggish the DAQ system will be.
4. The RAM tables can be editted through CAMAC commands (through the CAMAC FPGA to the rear/priority encoder FPGA). So can the NVRAM. However, this could take hours, depending on how sliggush the DAQ system will be.

Anode LCT Cards

JK: Altera tdf files, pcb files, pof files, test programs, and other documentation can be found here. Be sure to read the Readme.txt file.
 

LCT Mezzanine Cards

1. Old OSU cathode cards sent analog signals to a 48-channel mezzanine card which contained 6 8-channel Comparator ASIC #1 chips.
2. Old OSU anode cards and new CMU anode cards send 48 differential ECL signals to the 48-channel LCT card. For this, we built a 48-channel ECL receiver mezzanine card.
3. New OSU cathode preamp cards send analog signals to a piggy-back UCLA Comparator Card containing 6 16-channel Comparator ASIC #2 chips. This in turn sends 192 half-strip signals by way of differential ECL to (one or) two 96-channel ECL receiver mezzanine cards which are mounted on the "48-channel" LCT cards.

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