1998
Comparator ASIC and Board
Comparator ASIC "B"
There is a 16-channel comparator ASIC which was developed at CERN by
Jean-Claude
Santiard. This ASIC has significant advantages over the first-generation
8-channel ASIC. The comparators are simply time-over-threshold with no
digital logic. Most importantly, the offsets are much reduced: the RMS
of the offsets is expected to be about 0.9mV. The mean offset is adjustable
between 0.2mV and 5mV according to an external current. These comparators
put out three bits per strip: strip above threshold, strip larger than
neighbor on left, and left strip larger than right. The layout of these
5mm x 3mm chips:
90 chips total were produced. 10 chips were packaged in late January
1998. These 10 were tested and found to work well. At UCLA we received
6 chips in January and an additional 41 in late May 1998.
Comparator Card
The 96-channel Comparator Card plugs into the OSU DAQ card and receives
the analog Buckeye outputs with nominal 1 mV/fC transfer function and 150ns
peaking time (with chamber signals. The Comparator Card contains 4x buffer
amplifiers (to reduce the effect of comparator offsets), comparator ASICs
to handle A/D conversion, Altera 6010 FPGAs to produce L/R half-strip bits
from the raw comparator outputs, and Motorola 10124 TTL to ECL differential
drivers. In order to test the electronics under realistic noise and interference
conditions, the 96-channel comparator cards will be mounted on-chamber
as mezzanine cards on the OSU preamp/DAQ boards. The comparator cards receive
96+12=108 analog signals from the OSU cards, including the 12 shared signals
at the boundaries to allow seamless triggering. The comparators put out
three bits per strip: strip above threshold, strip larger than neighbor
on left, and left strip larger than right. Therefore, there will be 288
comparator chip outputs. This large number of signals will be reduced to
48 signals by clever, lossless data compression.
We take advantage of the slow development of cathode signals plus the
fact that there can only be one half-strip hit within any two strips (since
the hit strip has to have signal larger than either of its neighbors).
The 6:1 compression is accomplished by six Altera 10K20 FPGA chips on the
comparator card which form "triads". A triad is an output bit representing
hits on two adjacent strips: when a strip is found as the center of a cluster,
the triad is a time sequence of three bits. The first bit says that there
is a hit on the strip or its neighbor. The 2nd and 3rd bits give the 1/2-strip
position of the hit within the 2-strip wide unit. The signals are then
driven off of the comparator card using differential ECL drivers.
Here is a picture
of the comparator board layout. Careful - the file is really big (several
Mb). The 96-channel comparator card was developed by
H.C.
Shankar with help from
Yao Shi.
Shankar Chandramouly: Altera project and Byteblaster download files
in
one zipped
archive containing about 20 files, placed 6/6/98. (tdf files, pof files,
etc.) NOTE BENE: 24-Aug-2000 this link is dead. Shankar's old files can
be found on /usr/hep2/shankar area on the UCLA Sun cluster - not web-accessible.
Return to UCLA-CMS
trigger web page.
Page maintained by
Jay Hauser (hauser@physics.ucla.edu)
last updated 22 June 1999