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The output from all 12 Sector Processors is sent to a Muon Sorter (MS) which selects the 4 best muons out of 36 for transmission to the GMT.
The sorting is based on a 7-bit rank, which is provided by the SP. Higher ranks (i.e. larger 7-bit rank patterns) correspond to “better” muons for the purposes of sorting, so the MS selects the four muons with the largest rank and outputs them in descending order. The best muon should always be present on the 1st link to the GMT, the second best muon - on the 2nd link to the GMT and so on. The rest of the bits belonging to each incoming muon are stored in pipeline logic until the sorting result is obtained.
All sorting schemes are based on multiple comparisons and data multiplexing. Different design approaches and schemes require different number of comparison steps and number of comparisons at each step. Our main goal is to reduce the latency of sorting. We assume that latency is the time interval between the latching of input patterns into sorter chip and moment when the addresses of selected patterns are available for latching at the external logic outside sorter chip.